This U.S. nonprovisional patent application claims priority under 35 U.S.C. xc2xa7119 of Korean Patent Application 2002-32599, filed on Jun. 11, 2002, the entire contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to an analog synchronous mirror delay (ASMD) circuit, a method of generating a clock and an internal clock generator using the same.
2. Description of the Related Art
As the demand for a high-speed system increases, absence of skew between data and a system clock is more significant for exact transmissions of data. For example, a nonvolatile memory such as a synchronous dynamic random access memory (SDRAM) may typically include a clock generating circuit for generating an internal clock signal synchronizing with an external clock signal. Since many operations of an SDRAM including data input/output are with reference to the internal clock signal, the clock signal generating circuit which generates the internal clock signal is a more significant circuit to a SDRAM.
To substantially reduce the skew, internal clock generators, such as phase-locked loops (PLLs) and delay-locked loops (DLLs), are generally used. A phase-locked loop (PLL) or a delay-locked loop (DLL) is used to synchronize an internal clock signal with an external clock signal. For example, a PLL or DLL may use a feedback circuit within a SDRAM to generate an internal clock signal which derives from, and synchronizes with, an external clock signal.
The PLLs and DLLs have duty cycle correction schemes that may require several hundreds of clock cycles for locking. Further, the PLLs and the DLLs must be very precisely designed to properly operate regardless of variations in process, voltage, and temperature (PVT).
For synchronous DRAMs (SDRAMs) and dual data rate (DDR) SDRAMs, methods and/or circuits employing a synchronous mirror delay (SMD), an analog synchronous mirror delay (ASMD), and a single way pumping SMD have recently been developed, in an effort to synchronize an internal clock signal with an external clock signal. These delay circuits require two-clock cycles for locking. A duty cycle correction scheme is substantially significant in a dual edge triggering system, such as DDR synchronous DRAM; however, current SMD and ASMD circuits or methods, or clock generation circuits or methods including SMD or ASMD circuits, for example, do not include a duty cycle correction scheme.
Exemplary embodiments of the present invention provide an analog synchronous mirror delay (ASMD) with a two-clock cycle for locking and a duty cycle correction scheme, a method of generating a clock in ASMD that runs a duty cycle correction scheme and has a two-clock cycle for locking, and an internal clock generator using the analog synchronous mirror delay.
An exemplary embodiment of the present invention is directed to an analog synchronous mirror delay (ASMD) that may include a comparator with first and second input terminals that generates an output clock based on a comparison result between a signal on the first input terminal and a signal on the second input terminal, a first precharge circuit connected to the first input terminal and precharging the first input terminal and a second precharge circuit connected to the second input terminal and precharging the second input terminal. Additionally, the ASMD circuit may include a first discharge circuit discharging the first input terminal for a given period within a first cycle of an input clock, a first additional discharge circuit discharging the first input terminal for a first logic-state period of the input clock within first and second cycles of the input clock, a second discharge circuit discharging the second input terminal for the second cycle of the input clock, and a second additional discharge circuit discharging the second input terminal for a second logic-state period of the input clock within the first and second cycles of the input clock.
Another exemplary embodiment of the present invention is directed to a method of generating a clock that may include precharging a first node and a second node, discharging the first node for a given period of time within a first cycle of an input clock, discharging the first node for a given first logic-state period of the input clock, discharging the second node for a second cycle of the input clock, and discharging the second node for a given second logic-state period of the input clock. A signal output from the first node may be compared to a signal output from the second node, with an output clock being output based on a result of the comparison.
Another exemplary embodiment of the present invention is directed to an internal clock generator. The internal clock generator may include an input buffer buffering an external clock, an inverter inverting a signal output from the input buffer, and a plurality of ASMD circuits for generating clocks at different times, and an edge detector outputting an internal clock that rises at rising edges of certain clocks generated by the ASMD circuits and falls at rising edges of other certain clocks generated by the ASMD circuits. The internal clock generator may include first through fourth ASMD circuits. The first ASMD circuit may generate a first clock in response to the signal output from the input buffer, the first clock rising a given first time earlier than a rising edge of an odd numbered cycle of the signal output from the input buffer. The second ASMD circuit may operate one cycle later than the first ASMD circuit and may generate a second clock in response to the signal output from the input buffer, the second clock generated one cycle later than the first clock. The third ASMD circuit may generate a third clock in response to a signal output from the inverter, the third clock rising a given second time earlier than a rising edge of an odd numbered cycle of the signal output from the inverter. The fourth ASMD circuit may operate one cycle later than the third ASMD circuit and may generate a fourth clock in response to the signal output from the inverter, the fourth clock generated one cycle later than the third clock. The edge detector may output an internal clock that rises at rising edges of the first and second clocks and falls at rising edges of the third and fourth clocks.
Another exemplary embodiment of the present invention is directed to an analog synchronous mirror delay (ASMD) circuit that may include a comparator with first and second input terminals that generates an output clock based on a comparison result between a signal on the first input terminal and a signal on the second input terminal, a first precharge circuit connected to the first input terminal and precharging the first input terminal, and a second precharge circuit connected to the second input terminal and precharging the second input terminal. The ASMD circuit may also include a first pair of discharge circuits discharging the first input terminal within first and second cycles of the input clock, and a second pair of discharge circuits discharging the second input terminal within first and second cycles of the input clock.